Process Of Synthesis, Libraries And Technology Mapping:Introduction to synthesis, synthesizable and non synthesizable constructs. Logical synthesis of basic - combinational and sequential circuits.Synthesis Methodologies. Pre and post synthesis mismatch. Translation, mapping and optimization. Overview of Libraries: Target library, synthetic library, symbol library and link Library. Reading the design. Design constraints: design rule constraints and optimization constraints. Optimization for power, timing and area. Compile strategies in synthesis. Design analysis. Importance of wire load models. Specifying operating conditions and system interface characteristics - Advanced Synthesis flow:Post synthesis flow and analysis. Advanced critical path resynthesis, grouping and ungrouping the designs, cost priorities, optimization with timing and area efforts. Register retiming. Incremental, power and dft flows in synthesis - Timing Analysis:Introduction to timing concepts. Setup and hold times. Setup and hold time equalities and inequalities. Timing paths. Static timing delay calculation for basic flip flop & sequential circuits. Definition of timing path. Grouped timing paths. Timing path delay. Recovery and removal times. Pulse width, signal slew. Clock latency. Clock skew. Input arrival time. Output required time. Slack and critical path. False paths. Multi-cycle paths