Design of Digital Circuits and Computer Architecture

Overview The class provides an introduction to the design of digital circuitry. The class covers the basics of the technical foundations of gates. An introduction to hardware description languages and their use in the design process follows.

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Last updated Fri, 10-Jun-2022
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Course overview
Overview

The class provides an introduction to the design of digital circuitry. The class covers the basics of the technical foundations of gates. An introduction to hardware description languages and their use in the design process follows.

his class will be your first approach to Computer Architecture. You will study the design of digital circuits in order to:

  • understand the basics,
  • understand the principles (of design),
  • understand the precedents.

Based on such understanding, you will:

  • learn how a modern computer works underneath,
  • evaluate tradeoffs of different designs and ideas,
  • implement a principled design (a simple microprocessor),
  • learn to systematically debug increasingly complex systems,
  • hopefully develop novel, out-of-the-box designs.

    Lecture Details

    Design of Digital Circuits, ETH Zürich, Spring 2018 (https://safari.ethz.ch/digitaltechnik/)

    Lecture 1: Introduction and Basics
    Lecturer: Professor Onur Mutlu (http://people.inf.ethz.ch/omutlu)
    Date: February 22, 2018

    Slides (ppt): https://safari.ethz.ch/digitaltechnik/spring2018/lib/exe/fetch.php?media=digitaldesign-s18-lecture1-intro.ppt
    Slides (pdf): https://safari.ethz.ch/digitaltechnik/spring2018/lib/exe/fetch.php?media=digitaldesign-s18-lecture1-intro.pdf

The focus is on basics, principles, precedents, and how to use them to create/implement good designs.

Curriculum for this course
28 Lessons 39:26:26 Hours
Lecture
28 Lessons 39:26:26 Hours
  • Introduction and Basics
    Preview 01:29:38
  • Mysteries in Comp Arch
    01:26:19
  • Introduction to the Labs and FPGAs
    01:27:52
  • Mysteries in Comp Arch and Basics
    01:29:59
  • Combinational Logic
    01:30:24
  • Combinational Logic, HDL & Verilog
    01:36:27
  • Sequential Logic Design
    01:29:12
  • Timing and Verification
    01:12:55
  • Von Neumann Model, ISA, LC-3, MIPS
    01:30:10
  • ISA (II) and Assembly Programming
    01:32:36
  • Micro architecture
    01:36:40
  • Microarchitecture II
    01:30:11
  • Microprogramming
    01:35:29
  • Pipelining
    01:30:42
  • Pipelining Issues
    01:33:03
  • Out-of-Order Execution
    01:35:05
  • OoO, DataFlow, Superscalar Exec.
    01:23:47
  • Branch Prediction
    01:35:34
  • Branch Prediction II, VLIW, FGMT
    01:35:15
  • SIMD Processors
    01:34:46
  • SIMD Processors II and GPUs
    01:30:36
  • GPU Programming
    01:25:17
  • Systolic Arrays and Beyond
    01:06:36
  • Memory Organization & Technology
    00:28:10
  • Memory Hierarchy and Caches
    01:34:50
  • More Caches
    01:10:01
  • Virtual Memory
    00:24:16
  • Discussion Session
    01:30:36
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