Computer Architecture II

Overview Introduction and Basics - Fundamental Concepts and ISA - ISA Tradeoffs - More ISA Tradeoffs - ISA Wrap-Up, Single-Cycle- Multi-Cycle Microarchitecture - Microprogramming - Pipelining - Data Dependence Handling - Control Dependence Handling - Branch Prediction - Predication and Exceptions - State Maintenance & Recovery - Out-of-Order Execution - Data Flow and SIMD - Virtual Memory - SIMD and GPUs - GPUs, VLIW, Systolic Arrays - Static Instruction Scheduling - Memory Hierarchy - Caches - Advanced Caches - Main Memory and DRAM Basics - Memory Controllers & Scheduling - Memory Scheduling - Runahead Execution - Prefetching - Advanced Prefetching - Multiprocessors - Consistency & Coherence - Interconnects - Heterogeneous Multi-Core - Emerging Memory Tech

Beginner 0(0 Ratings) 0 Students enrolled English
Created by skill expert
Last updated Tue, 14-Jun-2022
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Course overview
Curriculum for this course
35 Lessons 57:16:02 Hours
Lecture
35 Lessons 57:16:02 Hours
  • Introduction and Basics
    01:31:29
  • Fundamental Concepts and ISA
    01:42:05
  • ISA Tradeoffs
    01:43:50
  • More ISA Tradeoffs
    Preview 01:41:57
  • ISA Wrap-Up, Single-Cycle
    01:41:17
  • Multi-Cycle Microarchitecture
    01:39:57
  • Microprogramming
    01:47:59
  • Pipelining
    01:40:44
  • Data Dependence Handling
    01:42:31
  • Control Dependence Handling
    01:44:04
  • Branch Prediction
    01:43:33
  • Predication and Exceptions
    01:44:13
  • State Maintenance & Recovery
    01:23:22
  • Out-of-Order Execution
    01:48:34
  • Data Flow and SIMD
    01:46:24
  • Virtual Memory 1
    01:06:50
  • Virtual Memory 2
    00:56:19
  • Virtual Memory 3
    01:12:18
  • SIMD and GPUs
    01:43:24
  • GPUs, VLIW, Systolic Arrays
    01:46:39
  • Static Instruction Scheduling
    01:50:03
  • Memory Hierarchy
    01:45:35
  • Caches
    01:37:43
  • Advanced Caches
    01:40:54
  • Main Memory and DRAM Basics
    01:35:15
  • Memory Controllers & Scheduling
    01:27:57
  • Memory Scheduling
    01:37:32
  • Runahead Execution
    01:37:30
  • Prefetching
    01:37:59
  • Advanced Prefetching
    01:45:52
  • Multiprocessors
    01:46:25
  • Consistency & Coherence
    01:45:49
  • Interconnects
    01:41:46
  • Heterogeneous Multi-Core
    01:43:20
  • Emerging Memory Tech
    01:34:53
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